Digital Design and Implementation with Field Programmable Devices

2005 ◽  
Author(s):  
Zainalabedin Navabi
Keyword(s):  
Digital Design ◽  
Design And Implementation ◽  
Field Programmable ◽  
Programmable Devices

scholarly journals Design and Implementation of Digital Filters for ECG Data Based on Field Programmable Gate Array and MATLAB

2020 ◽  
pp. 17-19
Author(s):  
Emre Cancioglu ◽  
Gokberk Cakiroglu ◽  
Alkim Gokcen ◽  
Yilmaz Sefa Altanay
Keyword(s):  
Digital Filters ◽  
Pass Band ◽  
System Generator ◽  
Design And Implementation ◽  
Field Programmable ◽  
Low Pass ◽  
Band Pass ◽  
Database Platform ◽  
High Pass ◽  
Ecg Data

This study provides design and implementation of four digital filters (low pass, high pass, band pass and band stop) for ECG (electrocardiogram) data on FPGA with MATLAB by a serial communication. The study is conducted with using ECG data which is obtained from PhysioBank Database platform. SysGen (System Generator for DSP) which is a toolbox for MATLAB is used for designing and implementing the digital filters. The aim of the study is to perform four different digital filters with various blocks on the SysGen Toolbox. The study then examines the results of four different digital filters.

The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

2012 ◽  
Vol 571 ◽  
pp. 534-537
Author(s):  
Bao Feng Zhang ◽  
De Hu Man ◽  
Jun Chao Zhu
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Distributed Algorithm ◽  
Design Method ◽  
Fir Filter ◽  
Experimental Results ◽  
Linear Phase ◽  
Design And Implementation ◽  
Field Programmable

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.

AN FPGA-BASED PLATFORM FOR A NETWORK ARCHITECTURE WITH DELAY GUARANTEE

2013 ◽  
Vol 22 (06) ◽  
pp. 1350045 ◽  
Author(s):  
MACIEJ WIELGOSZ ◽  
MAURITZ PANGGABEAN ◽  
JIANG WANG ◽  
LEIF ARNE RØNNINGEN
Keyword(s):  
Network Architecture ◽  
Multimedia Data ◽  
Low Latency ◽  
Traffic Condition ◽  
Network Nodes ◽  
Delay Guarantee ◽  
Design And Implementation ◽  
Platform Architecture ◽  
Delay Sensitive ◽  
Field Programmable

The background that underlies this work is the envisioned real-time tele-immersive collaboration system for the future that supports delay-sensitive applications involving participants from remote places via their collaboration spaces (CSs). The end-to-end delay as high as 20 ms is required for good synchronization of such applications, for example collaborative dancing and remote conducting of choir. It is much lower than that facilitated by existing teleconference systems. A novel network architecture with delay guarantee, namely Distributed Multimedia Plays (DMP), has been proposed and designed to realize the vision. The maximum low latency is guaranteed because DMP network nodes can drop DMP packets of multimedia data from the CSs due to instantaneous traffic condition. Besides ultrafast processing time, modularity, and scalability must be taken into account in hardware design and implementation of the nodes for seamless incorporation of the modules. These lead us to employing field-programmable gate array (FPGA) due to its substantial computational power and flexibility. This paper presents an FPGA-based platform for the design and implementation of DMP network nodes. It provides a detailed introduction to the platform architecture and the simulation-implementation environment for the design. The modularity of the implemented node is shown by addressing three important modules for packet dropping, 3D warping, and image transform. Our compact implementation of the network node on Xilinx Virtex-6 ML605 mostly consumes very small amount of available resources. Moreover the elementary operations on our implementation takes (much) less than 5 μs as desired to meet the low-latency requirement.

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