Aligning UML 2.0 State Machines and Temporal Logic for the Efficient Execution of Services

2006 ◽  
pp. 1613-1632 ◽  
Author(s):  
Frank Alexander Kraemer ◽  
Peter Herrmann ◽  
Rolv Bræk
Keyword(s):  
Temporal Logic ◽  
State Machines ◽  
Uml 2.0 ◽  
Efficient Execution

Formalization of UML state machines using temporal logic

2004 ◽  
Vol 3 (1) ◽  
pp. 31-54 ◽  
Author(s):  
Carlos Rossi ◽  
Manuel Enciso ◽  
Inmaculada P. de Guzmán
Keyword(s):  
Temporal Logic ◽  
State Machines ◽  
Uml State Machines

scholarly journals Closing the Gap Between Specification and Programming: VDM++ and Scala

10.29007/2w2f ◽  
2018 ◽  
Author(s):  
Klaus Havelund
Keyword(s):  
Temporal Logic ◽  
Programming Language ◽  
Runtime Verification ◽  
Specification Language ◽  
State Machines ◽  
Closing The Gap ◽  
High Level ◽  
Modern Programming Language

We argue that a modern programming language such as Scala offers a level of succinctness, which makes it suitable for program and systems specification as well as for high-level programming. We illustrate this by comparing the language with the VDM++ specification language. The comparison also identifies areas where Scala perhaps could be improved, inspired by VDM++. We furthermore illustrate Scala's potential as a specification language by augmenting it witha combination of parameterized state machines and temporal logic, defined as a library, thereby forming an expressive but simple runtime verification framework.

Institutionalising UML 2.0 state machines

2011 ◽  
Vol 7 (4) ◽  
pp. 315-323 ◽  
Author(s):  
Daniel Calegari ◽  
Nora Szasz
Keyword(s):  
State Machines ◽  
Uml 2.0

29 New Unclarities in the Semantics of UML 2.0 State Machines

2005 ◽  
pp. 52-65 ◽  
Author(s):  
Harald Fecher ◽  
Jens Schönborn ◽  
Marcel Kyas ◽  
Willem-Paul de Roever
Keyword(s):  
State Machines ◽  
Uml 2.0
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