scholarly journals Improving SHA-2 Hardware Implementations

2006 ◽  
pp. 298-310 ◽  
Author(s):  
Ricardo Chaves ◽  
Georgi Kuzmanov ◽  
Leonel Sousa ◽  
Stamatis Vassiliadis
Keyword(s):  
Hardware Implementations

scholarly journals Flexible and Transparent Memristive Synapse Based on Polyvinylpyrrolidone/N-doped Carbon Quantum Dot Nanocomposites for Neuromorphic Computing

2021 ◽  
Author(s):  
Tao Zeng ◽  
Zhi Yang ◽  
Jiabing Liang ◽  
Ya Lin ◽  
Yankun Cheng ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Neuromorphic Computing ◽  
Carbon Quantum Dot ◽  
Hardware Implementations

Memristive devices are widely recognized as promising hardware implementations of neuromorphic computing. Herein, a flexible and transparent memristive synapse based on polyvinylpyrrolidone (PVP)/N-doped carbon quantum dot (NCQD) nanocomposites through regulating...

EXPRESS: Design Considerations for Discrete Frequency Infrared Microscopy Systems

2021 ◽  
pp. 000370282110133
Author(s):  
Rohit Bhargava ◽  
Yamuna Dilip Phal ◽  
Kevin Yeh
Keyword(s):  
Imaging System ◽  
Chemical Imaging ◽  
Optical Component ◽  
Imaging Systems ◽  
Imaging Data ◽  
Discrete Frequency ◽  
Figures Of Merit ◽  
Design Considerations ◽  
Hardware Implementations ◽  
Measurement Capabilities

Discrete frequency infrared (DFIR) chemical imaging is transforming the practice of microspectroscopy by enabling a diversity of instrumentation and new measurement capabilities. While a variety of hardware implementations have been realized, considerations in the design of all-IR microscopes have not yet been compiled. Here we describe the evolution of IR microscopes, provide rationales for design choices, and the major considerations for each optical component that together comprise an imaging system. We analyze design choices in illustrative examples that use these components to optimize performance, under their particular constraints. We then summarize a framework to assess the factors that determine an instrument’s performance mathematically. Finally, we summarize the design and analysis approach by enumerating performance figures of merit for spectroscopic imaging data that can be used to evaluate the capabilities of imaging systems or suitability for specific intended applications. Together, the presented concepts and examples should aid in understanding available instrument configurations, while guiding innovations in design of the next generation of IR chemical imaging spectrometers.

scholarly journals A Review of Algorithms and Hardware Implementations for Spiking Neural Networks

2021 ◽  
Vol 11 (2) ◽  
pp. 23
Author(s):  
Duy-Anh Nguyen ◽  
Xuan-Tu Tran ◽  
Francesca Iacopi
Keyword(s):  
Neural Networks ◽  
Computational Cost ◽  
Superior Performance ◽  
Training Algorithms ◽  
Current State ◽  
Hardware Implementations ◽  
Neuromorphic Hardware ◽  
High Level ◽  
Event Based ◽  
Hardware Platforms

Deep Learning (DL) has contributed to the success of many applications in recent years. The applications range from simple ones such as recognizing tiny images or simple speech patterns to ones with a high level of complexity such as playing the game of Go. However, this superior performance comes at a high computational cost, which made porting DL applications to conventional hardware platforms a challenging task. Many approaches have been investigated, and Spiking Neural Network (SNN) is one of the promising candidates. SNN is the third generation of Artificial Neural Networks (ANNs), where each neuron in the network uses discrete spikes to communicate in an event-based manner. SNNs have the potential advantage of achieving better energy efficiency than their ANN counterparts. While generally there will be a loss of accuracy on SNN models, new algorithms have helped to close the accuracy gap. For hardware implementations, SNNs have attracted much attention in the neuromorphic hardware research community. In this work, we review the basic background of SNNs, the current state and challenges of the training algorithms for SNNs and the current implementations of SNNs on various hardware platforms.

Power Side-Channel Analysis of RNS GLV ECC Using Machine and Deep Learning Algorithms

2021 ◽  
Vol 21 (3) ◽  
pp. 1-20
Author(s):  
Mohamad Ali Mehrabi ◽  
Naila Mukhtar ◽  
Alireza Jolfaei
Keyword(s):  
Deep Learning ◽  
Elliptic Curve ◽  
Smart Cities ◽  
Information Leakage ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Public Key Cryptosystems ◽  
Elliptic Curve Cryptosystems ◽  
Hardware Implementations ◽  
Substantial Progress

Many Internet of Things applications in smart cities use elliptic-curve cryptosystems due to their efficiency compared to other well-known public-key cryptosystems such as RSA. One of the important components of an elliptic-curve-based cryptosystem is the elliptic-curve point multiplication which has been shown to be vulnerable to various types of side-channel attacks. Recently, substantial progress has been made in applying deep learning to side-channel attacks. Conceptually, the idea is to monitor a core while it is running encryption for information leakage of a certain kind, for example, power consumption. The knowledge of the underlying encryption algorithm can be used to train a model to recognise the key used for encryption. The model is then applied to traces gathered from the crypto core in order to recover the encryption key. In this article, we propose an RNS GLV elliptic curve cryptography core which is immune to machine learning and deep learning based side-channel attacks. The experimental analysis confirms the proposed crypto core does not leak any information about the private key and therefore it is suitable for hardware implementations.

Compact Hardware Implementations of MISTY1 Block Cipher

2017 ◽  
Vol 27 (03) ◽  
pp. 1850037 ◽  
Author(s):  
Yasir ◽  
Ning Wu ◽  
Xiaoqiang Zhang
Keyword(s):  
Low Power ◽  
Block Cipher ◽  
Comprehensive Analysis ◽  
The Other ◽  
Key Generation ◽  
Round Function ◽  
Other Hand ◽  
Hardware Implementations ◽  
Covered Area

This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO/FI function by re-utilizing S9/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds implementation. On the other hand, the proposed architecture 2 uses a single FO/FI function for both MISTY1 round function as well as extended key generation and can be employed for MISTY1 [Formula: see text] rounds. To analyze the performance and covered area for ASICs, Synopsys Design Complier, SMIC 0.18[Formula: see text][Formula: see text]m @ 1.8[Formula: see text]V is used. The hardware constituted 3041 and 2331 NAND gates achieving throughput of 171 and 166 Mbps for 8 rounds implementation of architectures 1 and 2, respectively. Comprehensive analysis of proposed designs is covered in this paper.

Sign in / Sign up

Export Citation Format

Share Document