System Level Multi-bank Main Memory Configuration for Energy Reduction

A preliminary study on system-level impact of persistent main memory

Thirteenth International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed.2012.6187478 ◽

2012 ◽

Cited By ~ 4

Author(s):

Taciano Perez ◽

Ney Laert Vilar Calazans ◽

Cesar A. F. De Rose

Keyword(s):

Main Memory ◽

System Level ◽

Preliminary Study

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Scheduler-based Multi-Bank Main Memory Configuration for Energy Reduction

2006 International Symposium on Industrial Embedded Systems ◽

10.1109/ies.2006.357460 ◽

2006 ◽

Author(s):

Hanene Ben Fradj ◽

Cecile Belleudy ◽

Michel Auguin

Keyword(s):

Main Memory ◽

Energy Reduction

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Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation

ACM Transactions on Embedded Computing Systems ◽

10.1145/3476838 ◽

2022 ◽

Vol 21 (1) ◽

pp. 1-25

Author(s):

Kazi Asifuzzaman ◽

Rommel Sánchez Verdejo ◽

Petar Radojković

Keyword(s):

Academic Research ◽

Random Access ◽

Power Estimation ◽

Spin Transfer Torque ◽

Main Memory ◽

System Level ◽

Next Generation ◽

Reliable System ◽

Novel Technology ◽

System Level Simulation

It is questionable whether DRAM will continue to scale and will meet the needs of next-generation systems. Therefore, significant effort is invested in research and development of novel memory technologies. One of the candidates for next-generation memory is Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). STT-MRAM is an emerging non-volatile memory with a lot of potential that could be exploited for various requirements of different computing systems. Being a novel technology, STT-MRAM devices are already approaching DRAM in terms of capacity, frequency, and device size. Although STT-MRAM technology got significant attention of various major memory manufacturers, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing and current parameters of this novel technology, which are required to perform a reliable main memory simulation on performance and power estimation. This study demonstrates an approach to perform a cycle accurate simulation of STT-MRAM main memory, being the first to release detailed timing and current parameters of this technology from academia—essentially enabling researchers to conduct reliable system-level simulation of STT-MRAM using widely accepted existing simulation infrastructure. The results show a fairly narrow overall performance deviation in response to significant variations in key timing parameters, and the power consumption experiments identify the key power component that is mostly affected with STT-MRAM.

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Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea11040036 ◽

2021 ◽

Vol 11 (4) ◽

pp. 36

Author(s):

Mohammad Nasim Imtiaz Khan ◽

Swaroop Ghosh

Keyword(s):

Data Privacy ◽

New Technologies ◽

Spin Transfer Torque ◽

Main Memory ◽

Security And Privacy ◽

System Level ◽

System Throughput ◽

Privacy And Security ◽

Von Neumann ◽

Privacy Issues

Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.

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