Systolic Architecture for Adaptive Censoring CFAR PI Detector

Large-Scale Scientific Computing - Lecture Notes in Computer Science ◽

10.1007/11666806_75 ◽

2006 ◽

pp. 655-662

Author(s):

Ivan Garvanov ◽

Christo Kabakchiev ◽

Plamen Daskalov

Keyword(s):

Systolic Architecture

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Systolic architecture for inverse discrete cosine transform

Electronics Letters ◽

10.1049/el:19951276 ◽

1995 ◽

Vol 31 (21) ◽

pp. 1809-1811 ◽

Cited By ~ 2

Author(s):

Yu-Tai Chang ◽

Chin-Liang Wang

Keyword(s):

Discrete Cosine Transform ◽

Systolic Architecture ◽

Cosine Transform ◽

Inverse Discrete Cosine Transform

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A modular systolic architecture for image convolutions

Proceedings of the 14th annual international symposium on Computer architecture - ISCA '87 ◽

10.1145/30350.30357 ◽

1987 ◽

Cited By ~ 4

Author(s):

K. Doshi ◽

P. Varman

Keyword(s):

Systolic Architecture

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A bit-level systolic architecture for implementing a VQ tree search

The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ◽

10.1007/bf00935212 ◽

1990 ◽

Vol 2 (3) ◽

pp. 149-158 ◽

Cited By ~ 7

Author(s):

M. Yan ◽

J. V. McCanny

Keyword(s):

Tree Search ◽

Systolic Architecture

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Time efficient systolic architecture for matrix vector multiplication

Information Processing Letters ◽

10.1016/0020-0190(87)90138-4 ◽

1987 ◽

Vol 24 (4) ◽

pp. 225-231

Author(s):

M. Zubair ◽

B.B. Madan

Keyword(s):

Systolic Architecture ◽

Matrix Vector Multiplication ◽

Matrix Vector

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Design and Implementation of a Systolic Architecture for Low Power Wireless Sensor Network

The Journal of the Korea institute of electronic communication sciences ◽

10.13067/jkiecs.2015.10.6.749 ◽

2015 ◽

Vol 10 (6) ◽

pp. 749-756 ◽

Cited By ~ 2

Author(s):

Kyung-Hoon Lee ◽

Hak-Jai Lee ◽

Young-Min Kim

Keyword(s):

Wireless Sensor Network ◽

Low Power ◽

Sensor Network ◽

Wireless Sensor ◽

Systolic Architecture ◽

Design And Implementation

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2-Dimensional systolic architecture for H.264/AVC variable block size motion estimation

International Conference on Circuits, Communication, Control and Computing ◽

10.1109/cimca.2014.7057753 ◽

2014 ◽

Author(s):

P. Jayakrishnan ◽

Harish. M. Kittur

Keyword(s):

Motion Estimation ◽

Block Size ◽

Systolic Architecture ◽

Variable Block

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A VLSI and WSI systolic architecture for multilayer feed-forward networks of arbitrary size

IJCNN-91-Seattle International Joint Conference on Neural Networks ◽

10.1109/ijcnn.1991.155574 ◽

2002 ◽

Author(s):

S. Barro ◽

A. Yanez

Keyword(s):

Systolic Architecture ◽

Feed Forward ◽

Arbitrary Size

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4-Bit Serial-Parallel Multiplier and Bit-Level Systolic Architecture for Implementation of Discrete Orthogonal Transforms

Communications in Computer and Information Science - Global Trends in Computing and Communication Systems ◽

10.1007/978-3-642-29219-4_11 ◽

2012 ◽

pp. 91-99

Author(s):

M. N. Murty ◽

S. S. Nayak ◽

B. Padhy ◽

S. N. Panda

Keyword(s):

Systolic Architecture ◽

Parallel Multiplier ◽

Discrete Orthogonal ◽

Orthogonal Transforms ◽

Bit Serial

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Novel flexible folded systolic architecture for symmetric FIR digital filters

2011 International Conference on Electric Information and Control Engineering ◽

10.1109/iceice.2011.5777495 ◽

2011 ◽

Author(s):

Guo Xuan ◽

Lu Qi-bin ◽

Du Wei-tao ◽

Yin Hang

Keyword(s):

Digital Filters ◽

Systolic Architecture ◽

Fir Digital Filters

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A systolic architecture for high speed hypergraph partitioning using a genetic algorithm

Progress in Evolutionary Computation - Lecture Notes in Computer Science ◽

10.1007/3-540-60154-6_51 ◽

1995 ◽

pp. 109-126 ◽

Cited By ~ 5

Author(s):

Heming Chan ◽

Pinaki Mazumder

Keyword(s):

Genetic Algorithm ◽

High Speed ◽

Systolic Architecture ◽

Hypergraph Partitioning

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