Field programmable gate array‐based all‐layer accelerator with quantization neural networks for sustainable cyber‐physical systems

2020 ◽  
Author(s):  
Jinyu Zhan ◽  
Xingzhi Zhou ◽  
Wei Jiang
Keyword(s):  
Neural Networks ◽  
Field Programmable Gate Array ◽  
Cyber Physical Systems ◽  
Physical Systems ◽  
Field Programmable ◽  
Gate Array

A Real-Time Deep Learning OFDM Receiver

2022 ◽  
Vol 15 (3) ◽  
pp. 1-25
Author(s):  
Stefan Brennsteiner ◽  
Tughrul Arslan ◽  
John Thompson ◽  
Andrew McCormick
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Orthogonal Frequency Division Multiplexing ◽  
Frequency Division Multiplexing ◽  
Frequency Division ◽  
Field Programmable ◽  
Gate Array ◽  
Fully Connected

Machine learning in the physical layer of communication systems holds the potential to improve performance and simplify design methodology. Many algorithms have been proposed; however, the model complexity is often unfeasible for real-time deployment. The real-time processing capability of these systems has not been proven yet. In this work, we propose a novel, less complex, fully connected neural network to perform channel estimation and signal detection in an orthogonal frequency division multiplexing system. The memory requirement, which is often the bottleneck for fully connected neural networks, is reduced by ≈ 27 times by applying known compression techniques in a three-step training process. Extensive experiments were performed for pruning and quantizing the weights of the neural network detector. Additionally, Huffman encoding was used on the weights to further reduce memory requirements. Based on this approach, we propose the first field-programmable gate array based, real-time capable neural network accelerator, specifically designed to accelerate the orthogonal frequency division multiplexing detector workload. The accelerator is synthesized for a Xilinx RFSoC field-programmable gate array, uses small-batch processing to increase throughput, efficiently supports branching neural networks, and implements superscalar Huffman decoders.

scholarly journals InSight: An FPGA-Based Neuromorphic Computing System for Deep Neural Networks

2020 ◽  
Vol 10 (4) ◽  
pp. 36
Author(s):  
Taeyang Hong ◽  
Yongshin Kang ◽  
Jaeyong Chung
Keyword(s):  
Neural Networks ◽  
Image Classification ◽  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
Deep Neural Networks ◽  
Computing System ◽  
Neuromorphic Computing ◽  
Neuromorphic Hardware ◽  
Field Programmable ◽  
Gate Array

Deep neural networks have demonstrated impressive results in various cognitive tasks such as object detection and image classification. This paper describes a neuromorphic computing system that is designed from the ground up for energy-efficient evaluation of deep neural networks. The computing system consists of a non-conventional compiler, a neuromorphic hardware architecture, and a space-efficient microarchitecture that leverages existing integrated circuit design methodologies. The compiler takes a trained, feedforward network as input, compresses the weights linearly, and generates a time delay neural network reducing the number of connections significantly. The connections and units in the simplified network are mapped to silicon synapses and neurons. We demonstrate an implementation of the neuromorphic computing system based on a field-programmable gate array that performs image classification on the hand-wirtten 0 to 9 digits MNIST dataset with 99.37% accuracy consuming only 93uJ per image. For image classification on the colour images in 10 classes CIFAR-10 dataset, it achieves 83.43% accuracy at more than 11× higher energy-efficiency compared to a recent field-programmable gate array (FPGA)-based accelerator.

Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

2008 ◽  
Author(s):  
Michael Wirthlin ◽  
Brent Nelson ◽  
Brad Hutchings ◽  
Peter Athanas ◽  
Shawn Bohner
Keyword(s):  
Field Programmable Gate Array ◽  
Fpga Design ◽  
Design Methodologies ◽  
Field Programmable ◽  
Gate Array
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