Dependability evaluation of integrated circuits at design time against laser fault injection

2011 ◽  
Vol 5 (5) ◽  
pp. 450-461
Author(s):  
Huiyun Li ◽  
Hai Yuan
Keyword(s):  
Integrated Circuits ◽  
Fault Injection ◽  
Design Time ◽  
Dependability Evaluation ◽  
Laser Fault Injection

Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation

2008 ◽  
Author(s):  
T. Kiyan ◽  
C. Boit ◽  
C. Brillert
Keyword(s):  
Laser Pulse ◽  
Integrated Circuits ◽  
Continuous Wave ◽  
Fault Injection ◽  
Scan Design ◽  
Flip Flop ◽  
Laser Stimulation ◽  
Scan Chain ◽  
P Type ◽  
Scan Pattern

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.

scholarly journals Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses

2015 ◽  
Author(s):  
Marc Lacruche ◽  
Nicolas Borrel ◽  
Clement Champeix ◽  
Cyril Roscian ◽  
Alexandre Sarafianos ◽  
...  
Keyword(s):  
Fault Injection ◽  
Nanosecond Pulses ◽  
Laser Fault Injection

scholarly journals Extensive Laser Fault Injection Profiling of 65 nm FPGA

2017 ◽  
Vol 1 (3) ◽  
pp. 237-251 ◽  
Author(s):  
Jakub Breier ◽  
Wei He ◽  
Shivam Bhasin ◽  
Dirmanto Jap ◽  
Samuel Chef ◽  
...  
Keyword(s):  
Fault Injection ◽  
Laser Fault Injection

A Program-Aware Fault-Injection Method for Dependability Evaluation Against Soft-Error Using Genetic Algorithm

2018 ◽  
Vol 27 (09) ◽  
pp. 1850144
Author(s):  
Bahman Arasteh
Keyword(s):  
Genetic Algorithm ◽  
Computer System ◽  
Fault Injection ◽  
Soft Errors ◽  
Soft Error ◽  
Injection Method ◽  
Software Failures ◽  
Input Program ◽  
Dependability Evaluation ◽  
Original Size

Decreasing the scale of transistors and exponential increase in the transistor counts has made the soft-errors as one of the major causes of software failures. Fault injection is a powerful method for dependability assessment of a computer system against soft-errors. A considerable number of randomly injected faults in the current methods and tools are effect-less or equivalent. To overcome this problem and reduce the cost of fault injection, this study presents a software based fault-injection method that accurately evaluates the dependability of a computer system with a limited number fault-injection. Using a genetic algorithm (GA) the most vulnerable executable paths of an input program is identified; then only the basic blocs (BBs) into the identified vulnerable paths are considered as the target of fault injection. The results of fault injections on the set of 8 traditional benchmark-programs show that the proposed method reduces about 20% of effect-less faults by avoiding the injection of faults in the error-derating blocks of a program. Furthermore, the number of injected faults is reduced to 60% of its original size in the random injection. Also, the proposed method provides more stable and accurate results than the random injection.

Backside Shield against Physical Attacks for Secure ICs.

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-15
Author(s):  
Stéphan BOREL ◽  
Edouard DESCHASEAUX ◽  
Jean CHARBONNIER ◽  
Philippe MEDINA ◽  
Stéphanie ANCEAU ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Fault Injection ◽  
Micro Milling ◽  
Test Vehicle ◽  
Laser Illumination ◽  
Confidential Data ◽  
The World ◽  
Protection Layer ◽  
Deep Cavities ◽  
Electrical Characterizations

Although the implementation of multiple countermeasures, both hardware and software, are making integrated circuits more and more secure, the backside of a chip is still considered as a vulnerability regarding physical attacks. A novel protection structure will be presented here, which consists in combining several elements to make it impossible for a hacker to use the backside of a chip as an access to the active parts of the IC without triggering an alert. The integration flow is using standard processes coming from the world of packaging and it is applied on commonly available industrial tools. Cybersecurity by hardware can thus be implemented at low additional cost. In order to weaken the chip in case of milling, deep cavities are etched into the substrate. They are lined with a 3D metallic shield that block the IR wavelengths commonly used for fault injection. This part of the structure is fabricated using standard TSV last process steps. These cavities are then corked with a polymer so that RDL-like metallic serpentines connected to TSVs can meander all over the protected area. This constitutes the active part of the shield, since the integrity of the serpentines can be controlled by measuring their electrical resistance. Finally the structure is covered with a thick protection layer with specific properties: it is FIB-resistant and fully opaque to IR. In order to evaluate the efficiency of the countermeasures, a test vehicle has been designed and fabricated with metal pads on one side and with the protection structure on the other side. The backside process was done using a glass carrier in order to handle the wafers after thinning below 200μm. After debonding, the wafers were tested and singulated before being hacked. A realistic scenario of physical attacks will be presented together with the physical, optical and electrical characterizations after the different attacks including (P)FIB ablation, micro-milling, chemical etching and laser illumination. We will conclude on the interest of such a structure for IoT or other applications that require protecting confidential data.

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