scholarly journals NovelQ-factor enhancement technique for on-chip spiral inductors and its application to cmos low-noise amplifier designs

2015 ◽  
Vol 57 (12) ◽  
pp. 2883-2886 ◽  
Author(s):  
Fanyi Meng ◽  
Kaixue Ma ◽  
Kiat Seng Yeo ◽  
Shanshan Xu
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Enhancement Technique ◽  
Spiral Inductors ◽  
Noise Amplifier ◽  
On Chip

scholarly journals 4–20 GHz low noise amplifier MMIC with on-chip switchable gate biasing circuit

2017 ◽  
Vol 14 (18) ◽  
pp. 20170711-20170711 ◽  
Author(s):  
Wei Chen ◽  
Zhiyu Wang ◽  
Hua Chen ◽  
Zhengliang Huang ◽  
Jiongjiong Mo
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Noise Amplifier ◽  
On Chip

An ESD Protected Wideband CMOS Low Noise Amplifier Employing Active Feedback Technique

2011 ◽  
Vol 403-408 ◽  
pp. 2809-2813
Author(s):  
Kuan Bao ◽  
Xiang Ning Fan
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Fully Integrated ◽  
Input Matching ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
On Chip

This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic and input matching are simultaneously achieved by active-feedback technique. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Implemented in 0.18-μm CMOS process, the core size of the fully integrated LNA circuits is 535 μm×425 μm without any passive on-chip inductor. The simulated gain and the minimal noise figure of the CMOS LNA are 17.5 dB and 2.0 dB, respectively. The LNA achieves a -3dB bandwidth of 3.1 GHz. And the simulated IIP3 is -4.4 dBm at 2.5 GHz. Operating at 1.8V, the LNA draws a current of 7.7 mA.

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