46-W high efficiency unbalanced doherty power amplifier in extended output power back-off

2012 ◽  
Vol 54 (7) ◽  
pp. 1612-1614 ◽  
Author(s):  
Dong-Hee Jang ◽  
Ji-Yeon Kim ◽  
Jong-Heon Kim
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Efficiency ◽  
Doherty Power Amplifier

scholarly journals A Power Amplifier with Large High-Efficiency Range for 5G Communication

Sensors ◽  
2020 ◽  
Vol 20 (19) ◽  
pp. 5581
Author(s):  
Zhiwei Zhang ◽  
Zhiqun Cheng ◽  
Guohua Liu
Keyword(s):  
Output Power ◽  
Design Process ◽  
Power Amplifier ◽  
High Efficiency ◽  
New Method ◽  
Saturated Output Power ◽  
Doherty Power Amplifier ◽  
5G Communication

This paper presents a new method to design a Doherty power amplifier (DPA) with a large, high-efficiency range for 5G communication. This is through analyzing the drain-to-source capacitance (CDS) of DPAs, and adopting appropriate impedance of the peak device. A closed design process is proposed, to design the extended efficiency range DPA based on derived theories. For validation, a DPA with large efficiency range was designed and fabricated by using two equal devices. The measured results showed that the saturated output power was between 43.4 dBm and 43.7 dBm in the target band. Around 70% saturated drain efficiency is obtained with a gain of greater than 11 dB. Moreover, the obtained drain efficiency is larger than 50% at the 10 dB power back-off, when operating at 3.5 GHz. These superior performances illustrate that the implemented DPA can be applied well in 5G communication.

scholarly journals High efficiency Doherty power amplifier based on asymmetrical matching network

2021 ◽  
Vol 23 (2) ◽  
pp. 910
Author(s):  
Mussa Mabrok ◽  
Zahriladha Zakaria ◽  
Tole Sutikno
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Communication Systems ◽  
High Efficiency ◽  
Design Strategy ◽  
Matching Network ◽  
High Data ◽  
Fifth Generation ◽  
Data Rates ◽  
Doherty Power Amplifier

Doherty power amplifier (DPA) with high efficiency at the output power back off is highly demanded for modern wireless communication systems to achieve high data rates and reduce the power consumption and operation costs. This paper presents a new design strategy for enhancing DPA’s back-off efficiency. New design strategy called asymmetrical matching network is used to achieve asymmetric operation, which helps to compensate for the low power delivered by the peaking stage in the conventional DPA. The simulation results showed an enhancement in the back-off efficiency, where the proposed design is able toachieve 46-52% drain efficiency at 8 dB output power back-off while maintains high efficiency of 73-80 % at saturation over the designed bandwidth of 3.4-3.6 GHz. The proposed design is suitable for high efficiency sub-6 GHz fifth-generation wireless applications.<br /><div> </div>

scholarly journals Design and simulate a doherty power amplifier using GaAs technology for telecommunication applications

2019 ◽  
Vol 15 (2) ◽  
pp. 845
Author(s):  
Ehsan Barmala
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Power Amplifiers ◽  
High Efficiency ◽  
Maximum Output Power ◽  
Input Power ◽  
Power Divider ◽  
Maximum Efficiency ◽  
Maximum Output ◽  
Doherty Power Amplifier

<span>In this paper, a Doherty power amplifier was designed and simulated at 2.4 GHz central frequency which has high efficiency. A Doherty power amplifier is a way to increase the efficiency in the power amplifiers. OMMIC ED02AH technology and PHEMT transistors, which is made of gallium arsenide, have been used in this simulation. The Doherty power amplifier unique feature is its simple structure which is consisting of two parallel power amplifiers and transmission lines. In order to integrate the circuit, the Doherty power transmission amplifier lines were implemented using an inductor and capacitive components. Also, the Wilkinson power divider is used on the chip input. To improve the efficiency, the auxiliary amplifier dimensions is selected enlarge and the further input power is allocated it by the power divider. A parallel R-C circuit has been used at the input of transistors to improve their stability. Simulation results show that the Doherty power amplifier has 17.2 dB output power gain, 23 dBm maximum output power, and its output power P<sub>1dB</sub> =22.6dBm at compression point -1 dB, also, its maximum efficiency is 55.5%.</span>

scholarly journals Design of a Wideband Doherty Power Amplifier with High Efficiency for 5G Application

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 873
Author(s):  
Abbas Nasri ◽  
Motahhareh Estebsari ◽  
Siroos Toofan ◽  
Anna Piacibello ◽  
Marco Pirola ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Efficiency ◽  
Matching Network ◽  
Class Ab ◽  
Measurement Results ◽  
Saturated Output Power ◽  
Doherty Power Amplifier ◽  
Good Trade ◽  
The Impact

This paper discusses the design of a wideband class AB-C Doherty power amplifier suitable for 5G applications. Theoretical analysis of the output matching network is presented, focusing on the impact of the non-ideally infinite output impedance of the auxiliary amplifier in back off, due to the device’s parasitic elements. By properly accounting for this effect, the designed output matching network was able to follow the desired impedance trajectories across the 2.8 GHz to 3.6 GHz range (fractional bandwidth = 25%), with a good trade-off between efficiency and bandwidth. The Doherty power amplifier was designed with two 10 W packaged GaN HEMTs. The measurement results showed that it provided 43 dBm to 44.2 dBm saturated output power and 8 dB to 13.5 dB linear power gain over the entire band. The achieved drain efficiency was between 62% and 76.5% at saturation and between 44% and 56% at 6 dB of output power back-off.

1-Package 500W High Efficiency LDMOS Doherty Power Amplifier

2018 ◽  
Author(s):  
Jean-Christophe Nanan ◽  
Yuanyuan Dong ◽  
Sandra De Meyer ◽  
Damien Scatamacchia
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Doherty Power Amplifier

A 4.2-to-5.4 GHz stacked GaAs HBT power amplifier for C-band applications

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 243-248
Author(s):  
Min Liu ◽  
Panpan Xu ◽  
Jincan Zhang ◽  
Bo Liu ◽  
Liwen Zhang
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Power ◽  
High Efficiency ◽  
Common Source ◽  
Power Performance ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Saturated Output Power

Purpose Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications. Design/methodology/approach A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks. Findings By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz. Originality/value The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

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