Low power concurrent compact dual-band receiver front-end using 0.18-μm CMOS process

2009 ◽  
Vol 51 (6) ◽  
pp. 1527-1530
Author(s):  
Kuo-Hua Cheng
Keyword(s):  
Low Power ◽  
Dual Band ◽  
Cmos Process ◽  
Front End

scholarly journals A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis

2018 ◽  
Vol 8 (3) ◽  
pp. 27 ◽  
Author(s):  
Avish Kosari ◽  
Jacob Breiholz ◽  
NingXi Liu ◽  
Benton Calhoun ◽  
David Wentzloff
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Low Noise ◽  
Signal Acquisition ◽  
Cmos Process ◽  
Ecg Signal ◽  
Ecg Monitoring ◽  
Power Circuit ◽  
Front End ◽  
Analog Front End

This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of ECG signal acquisition systems. The AFE was realized with a three-stage fully differential AC-coupled amplifier, and it provides bio-signal acquisition with programmable gain and bandwidth. The AFE was implemented in a 130 nm CMOS process, and it has a measured tunable mid-band gain from 31 to 52 dB with tunable low-pass and high-pass corner frequencies. Under only 0.5 V supply voltage, it consumes 68 nW of power with an input-referred noise of 2.8 µVrms and a power efficiency factor (PEF) of 3.9, which makes it very suitable for energy-harvesting applications. The low-noise 68nW AFE was also integrated on a self-powered physiological monitoring System on Chip (SoC) that is used to capture ECG bio-signals. Heart rate extraction (R-R) detection algorithms were implemented and utilized to analyze the ECG data received by the AFE, showing the feasibility of <100 nW AFE for continuous ECG monitoring applications.

scholarly journals An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1760
Author(s):  
Folla Kamdem Jérôme ◽  
Wembe Tafo Evariste ◽  
Essimbi Zobo Bernard ◽  
Maria Liz Crespo ◽  
Andres Cicuttin ◽  
...  
Keyword(s):  
Low Power ◽  
High Throughput ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
High Luminosity ◽  
Gain Bandwidth ◽  
Wide Bandwidth ◽  
Ultra Low Power ◽  
Front End

The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

A low power dual-band multi-mode RF front-end for GNSS applications

2010 ◽  
Vol 31 (11) ◽  
pp. 115008
Author(s):  
Hao Zhang ◽  
Zhiqun Li ◽  
Zhigong Wang
Keyword(s):  
Low Power ◽  
Dual Band ◽  
Front End ◽  
Rf Front End ◽  
Multi Mode

A LOW-NOISE LOW-POWER FRONT-END AMPLIFIER FOR NEURAL-RECORDING APPLICATIONS

2010 ◽  
Vol 22 (04) ◽  
pp. 301-306 ◽  
Author(s):  
Mohammad Hossein Zarifi ◽  
Javad Frounchi ◽  
Mohammad A. Tinati ◽  
Shahin Farshchi ◽  
Jack W. Judy
Keyword(s):  
Low Power ◽  
Heat Dissipation ◽  
Harmonic Distortion ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Fully Differential ◽  
Front End

Monitoring the electrical activities of a large number of neurons in vertebrates' central nervous system in vivo through hundreds of parallel channels without interferring in their natural functions is a neuroscientist's interest. Value of this information in both scientific and clinical contexts, especially in expansion of brain–computer interfaces, is extremely significant. Therefore, low-noise amplifiers are needed with filtering capability on the front end to amplify the desired signals and eliminate direct current baseline shifts. Hence, size and power consumption need to be minimized to reduce trauma and heat dissipation, which can result in tissue damage for human applications and the system needs to be implantable and wireless. The practical solution for developing such systems is system-on-a-chip, based on ultra-low-power mixed-mode and wideband RFIC designs. They, however, impose a number of challenges that may require nontraditional solutions. In this paper, we present a fully differential low-power low-noise preamplifier suitable for recording biological signals, from a few mHz up to 10 kHz. This amplifier has a bandpass filter that is tunable between 10 mHz and 10 kHz, and has been designed and simulated in a standard 90-nm CMOS process. The circuit consumes 10 μW from a 1.2 V supply and provides a gain of 40 dB and an output swing of ±0.5 V with a total harmonic distortion of less than 0.5%. The total input-referred noise level is 4.6 μV integrating the noise over 0.01 Hz to 10 kHz.

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