Dual-band aperture-coupled rectenna for radio frequency energy harvesting

2019 ◽  
Vol 29 (1) ◽  
pp. e21651 ◽  
Author(s):  
Faza S. Mohd Noor ◽  
Zahriladha Zakaria ◽  
Herwansyah Lago ◽  
Maizatul A. Meor Said
Keyword(s):  
Energy Harvesting ◽  
Radio Frequency ◽  
Dual Band ◽  
Radio Frequency Energy

A dual‐band high‐gain quasi‐Yagi antenna with split‐ring resonators for radio frequency energy harvesting

2019 ◽  
Vol 61 (9) ◽  
pp. 2174-2181 ◽  
Author(s):  
Zhicong Chen ◽  
Miaowang Zeng ◽  
Andrey S. Andrenko ◽  
Yongzhao Xu ◽  
Hong‐Zhou Tan
Keyword(s):  
Energy Harvesting ◽  
Radio Frequency ◽  
High Gain ◽  
Ring Resonators ◽  
Dual Band ◽  
Split Ring ◽  
Split Ring Resonators ◽  
Radio Frequency Energy ◽  
Yagi Antenna

A Dual Frequency RF-DC Rectifier Circuit with a Low Input Power for Radio Frequency Energy Harvesting

2019 ◽  
Vol 28 (03) ◽  
pp. 1950048 ◽  
Author(s):  
Mohamed Mokhlès Mnif ◽  
Hassene Mnif ◽  
Mourad Loulou
Keyword(s):  
Energy Harvesting ◽  
Radio Frequency ◽  
Threshold Voltage ◽  
Output Voltage ◽  
Alternative Energy ◽  
Input Power ◽  
Design System ◽  
Low Input ◽  
Rectifier Circuit ◽  
Radio Frequency Energy

The energy-harvesting radio frequency (RF) can be an attractive alternative energy capable of replacing all or some of the board batteries. The RF waves are present in several high frequencies ([Formula: see text] GHz) and at low power (a few [Formula: see text]W). An energy-harvesting circuit designed must provide 1[Formula: see text]V voltage at minimum that is able to operate an actuator or a sensor. The RF-DC rectifier is the main component of an energy-harvesting circuit. This paper presents a new design RF-DC rectifier circuit using the MOSFET transistors, the capacitors and the inductors. Our proposed circuit is a combination of an Inductor–Capacitor–Inductor–Capacitor (LCLC) serie-parallel resonant tank (SPRT) and rectifier cascade using the Dynamic threshold Voltage Cancellation (DVC) and the technique of the Internal threshold Voltage Cancellation (IVC). Our proposed circuit operates in dual frequencies [Formula: see text][Formula: see text]GHz and [Formula: see text][Formula: see text]GHz with a low input power [Formula: see text][Formula: see text][Formula: see text]W ([Formula: see text][Formula: see text]dbm) and [Formula: see text][Formula: see text][Formula: see text]W ([Formula: see text][Formula: see text]dbm), respectively. This circuit gives a Power Conversion Efficiency (PCE) of 56.9% and an output voltage [Formula: see text][Formula: see text]V for the frequency 2.543[Formula: see text]GHz and a PCE of 62.6% and an output voltage [Formula: see text][Formula: see text]V for the frequency 4[Formula: see text]GHz. The pre-layout simulations were performed using the Advanced Design System (ADS) and the technology used is CMOS 0.18[Formula: see text][Formula: see text]m from TSMC. The simulations were performed on the proposed circuit composed by three stages.

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