A multigrid method with reduced phase error for 2D damped Helmholtz equations

2021 ◽  
Author(s):  
Mostak Ahmed ◽  
Chengjian Zhang
Keyword(s):  
Multigrid Method ◽  
Phase Error ◽  
Helmholtz Equations

RF Phase Error Built-In-Self-Test for A GSM SOC

2008 ◽  
Vol 1 (4) ◽  
pp. 39-44
Author(s):  
Dallas Webster ◽  
Loi Phan ◽  
Oren Eliezer ◽  
Rick Hudgens ◽  
Donald Lie
Keyword(s):  
Phase Error ◽  
Self Test ◽  
Built In Self Test

РАЗРАБОТКА СВЧ МОНОЛИТНЫХ ИНТЕГРАЛЬНЫХ СХЕМ МИЛЛИМЕТРОВОГО ДИАПАЗОНА НА ОСНОВЕ GAAS ДЛЯ ПРИМЕНЕНИЯ В СОВРЕМЕННЫХ ИНФОРМАЦИОННОКОММУНИКАЦИОННЫХ СИСТЕМАХ НОВОГО ПОКОЛЕНИЯ (5G)

2020 ◽  
Vol 96 (3s) ◽  
pp. 321-324
Author(s):  
Е.В. Ерофеев ◽  
Д.А. Шишкин ◽  
В.В. Курикалов ◽  
А.В. Когай ◽  
И.В. Федин
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Integrated Circuit ◽  
Phase Shifter ◽  
Phase Error ◽  
Microwave Integrated Circuit ◽  
Gain Compression ◽  
Monolithic Microwave Integrated Circuit ◽  
And Performance ◽  
Power Capability

В данной работе представлены результаты разработки СВЧ монолитной интегральной схемы шестиразрядного фазовращателя и усилителя мощности диапазона частот 26-30 ГГц. СКО ошибки по фазе и амплитуде фазовращателя составили 1,2 град. и 0,13 дБ соответственно. Максимальная выходная мощность и КПД по добавленной мощности усилителя в точке сжатия Ку на 1 дБ составили 30 дБм и 20 % соответственно. This paper describes the design, layout, and performance of 6-bit phase shifter and power amplifier monolithic microwave integrated circuit (MMIC), 26-30 GHz band. Phase shifter MMIC has RMS phase error of 1.2 deg. And RMD amplitude error is 0.13 dB. MMIC power amplifier has output power capability of 30 dBm at 1 dB gain compression (P-1dB) and PAE of 20 %.

FM-CW Signal Phase Error Analysis and Compensation

2015 ◽  
Author(s):  
Y. Deng ◽  
X. Guo ◽  
R. Wang ◽  
C. Hu ◽  
T. Zeng
Keyword(s):  
Error Analysis ◽  
Phase Error ◽  
Signal Phase

scholarly journals Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 231
Author(s):  
Chester Sungchung Park ◽  
Sunwoo Kim ◽  
Jooho Wang ◽  
Sungkyung Park
Keyword(s):  
Integrated Circuit ◽  
Building Block ◽  
Orthogonal Frequency Division Multiplexing ◽  
Critical Path ◽  
Phase Error ◽  
System Level ◽  
Comb Filter ◽  
Carrier Aggregation ◽  
Path Delay ◽  
Front End

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

scholarly journals A Calibration Method of Phase Error Caused by Target’s Position Error

2021 ◽  
Vol 187 ◽  
pp. 188-193
Author(s):  
Fang Liu ◽  
Ming Lyn ◽  
Haohao Hou
Keyword(s):  
Phase Error ◽  
Calibration Method ◽  
Position Error
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