A CNT based VCO with extremely low phase noise and wide frequency range for PLL application

2021 ◽  
Author(s):  
Hamed Sarbazi ◽  
Reza Sabbaghi‐Nadooshan ◽  
Alireza Hassanzadeh
Keyword(s):  
Phase Noise ◽  
Wide Frequency Range ◽  
Frequency Range ◽  
Low Phase Noise

scholarly journals An integer-N frequency synthesizer for medical implantable devices

2021 ◽  
Author(s):  
Nima Haghighi
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Frequency Synthesizer ◽  
Wide Frequency Range ◽  
Implantable Devices ◽  
Total Power ◽  
Frequency Range ◽  
Phase Frequency Detector ◽  
Frequency Detector ◽  
Low Phase Noise

This thesis proposes an Integer-N frequency synthesizer in TSMC 0.18µm technology. The design is aimed for MICS (Medical Implantable Communication Services) devices operating at 402-406 MHz. A low phase noise, wide frequency range Quadrature Voltage Controlled Oscillator (QVCO) has been designed and simulated. The simulated phase noise @ 160 KHz offset is -100.3 dBc/Hz with the power consumption of 0.9 mW. This design addresses the small size, low phase noise and low power requirements for the Implantable devices. A wide frequency range Source Coupled Logic (SCL)32/33 prescaler divider has been designed. The program counter and Swallow counter have been implemented in Verilog-A which allow a division ratio of 2690 from the output of the QVCO. A phase frequency detector based on a modified TSPC D-Flip Flop is designed, which leads to a faster response time. The phase frequency detector, the charge pump, and the loop filter would consume 0.5 mW power. The total power consumption of the synthesizer is at 4.6 mW with 2% steady state settlement time of 160 μs.

scholarly journals An integer-N frequency synthesizer for medical implantable devices

2021 ◽  
Author(s):  
Nima Haghighi
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Frequency Synthesizer ◽  
Wide Frequency Range ◽  
Implantable Devices ◽  
Total Power ◽  
Frequency Range ◽  
Phase Frequency Detector ◽  
Frequency Detector ◽  
Low Phase Noise

This thesis proposes an Integer-N frequency synthesizer in TSMC 0.18µm technology. The design is aimed for MICS (Medical Implantable Communication Services) devices operating at 402-406 MHz. A low phase noise, wide frequency range Quadrature Voltage Controlled Oscillator (QVCO) has been designed and simulated. The simulated phase noise @ 160 KHz offset is -100.3 dBc/Hz with the power consumption of 0.9 mW. This design addresses the small size, low phase noise and low power requirements for the Implantable devices. A wide frequency range Source Coupled Logic (SCL)32/33 prescaler divider has been designed. The program counter and Swallow counter have been implemented in Verilog-A which allow a division ratio of 2690 from the output of the QVCO. A phase frequency detector based on a modified TSPC D-Flip Flop is designed, which leads to a faster response time. The phase frequency detector, the charge pump, and the loop filter would consume 0.5 mW power. The total power consumption of the synthesizer is at 4.6 mW with 2% steady state settlement time of 160 μs.

scholarly journals Low Phase Noise and Wide-Range Class-C VCO Using Auto-Adaptive Bias Technique

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1290
Author(s):  
Jeong-Yun Lee ◽  
Gwang Sub Kim ◽  
Goo-Han Ko ◽  
Kwang-Il Oh ◽  
Jae Gyeong Park ◽  
...  
Keyword(s):  
Phase Noise ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Wide Frequency Range ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Frequency Range ◽  
Wide Range ◽  
Class C ◽  
Low Phase Noise

This paper proposes a new structure of 24-GHz class-C voltage-controlled oscillator (VCO) using an auto-adaptive bias technique. The VCO in this paper uses a digitally controlled circuit to eliminate the possibility of start-up failure that a class-C structure can have and has low phase noise and a wide frequency range. To expand the frequency tuning range, a 3-bit cap-bank is used and a triple-coupled transformer is used as the core inductor. The proposed class-C VCO implements a 65-nm RF CMOS process. It has a phase noise performance of −105 dBc/Hz or less at 1-MHz offset frequency and the output frequency range is from 22.8 GHz to 27.3 GHz, which consumes 8.3–10.6 mW of power. The figure-of-merit with tuning range (FoMT) of this design reached 191.1 dBc/Hz.

Design of A 3-10 GHz Low Phase Noise YIG-Tuned Oscillator

2011 ◽  
Vol 130-134 ◽  
pp. 1374-1378
Author(s):  
Deng Bao Li ◽  
Wan Shun Jiang
Keyword(s):  
Phase Noise ◽  
Test Data ◽  
Power Output ◽  
Yttrium Iron Garnet ◽  
Noise Model ◽  
Frequency Range ◽  
Yttrium Iron ◽  
Oscillation Phase ◽  
Iron Garnet ◽  
Low Phase Noise

In this paper, a YIG-tuned oscillator with low phase noise is designed successfully, the frequency range of 3 to 10 GHz, which is based on the theory of oscillation phase noise model and yttrium iron garnet (YIG) sphere’s characteristic. Its typical measure phase noise is-123.3 dBc at 100 kHz offset and-141.2 dBc/Hz at 1 MHz and-148 dBc/Hz at 10 MHz from carrier, and its minimum power output is more than 13 dBm across most of the band. The approach used to design the oscillator circuit will be discussed and test data will be presented.

Octave Frequency Range Triple-band Low Phase Noise K/Ka-Band VCO with a New Dual-path Inductor

2020 ◽  
Author(s):  
Md Aminul Hoque ◽  
Mohammad Chahardori ◽  
Pawan Agarwal ◽  
Mohammad Ali Mokri ◽  
Deukhyoun Heo
Keyword(s):  
Phase Noise ◽  
Frequency Range ◽  
Ka Band ◽  
Low Phase Noise ◽  
Triple Band

A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology

2019 ◽  
Vol 29 (09) ◽  
pp. 2050142
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Charge Pump ◽  
Cmos Technology ◽  
Wide Frequency Range ◽  
Phase Detector ◽  
Total Power ◽  
Control Voltage ◽  
Frequency Range ◽  
Wide Range ◽  
Low Jitter

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6[Formula: see text]GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-[Formula: see text][Formula: see text]m CMOS technology with supply voltage of 1.8[Formula: see text]V. The output clocks with cycle-to-cycle jitter of 2.13[Formula: see text]ps at 1.6[Formula: see text]GHz. The phase noise of VCO is [Formula: see text]137[Formula: see text]dBc/Hz at an offset of 100[Formula: see text]MHz and total power consumed by the proposed PLL is 2.63[Formula: see text]mW at 1.6[Formula: see text]GHz.

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