Impact of high
            k
            spacer on RF stability performance of double gate junctionless transistor

Veerati Raju; K. Sivasankaran

doi:10.1002/jnm.2481

Impact of high k spacer on RF stability performance of double gate junctionless transistor

International Journal of Numerical Modelling Electronic Networks Devices and Fields ◽

10.1002/jnm.2481 ◽

2018 ◽

Vol 32 (1) ◽

pp. e2481 ◽

Cited By ~ 2

Author(s):

Veerati Raju ◽

K. Sivasankaran

Keyword(s):

Double Gate ◽

Stability Performance ◽

High K ◽

Junctionless Transistor

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Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-K Dielectrics and Gate Metals

Silicon ◽

10.1007/s12633-020-00669-x ◽

2020 ◽

Author(s):

Achinta Baidya ◽

T. R. Lenka ◽

S. Baishya

Keyword(s):

Double Gate ◽

High K ◽

Distortion Analysis ◽

Junctionless Transistor

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Impact of High-k spacer and Negative Capacitance on Double Gate Junctionless Transistor for Improved Short Channel Immunity and Reliability

2018 4th International Conference on Devices, Circuits and Systems (ICDCS) ◽

10.1109/icdcsyst.2018.8605167 ◽

2018 ◽

Cited By ~ 1

Author(s):

Hema Mehta ◽

Harsupreet Kaur

Keyword(s):

Negative Capacitance ◽

Double Gate ◽

Short Channel ◽

High K ◽

Junctionless Transistor

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Impact of thin high-k dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor

Materials Science in Semiconductor Processing ◽

10.1016/j.mssp.2017.08.031 ◽

2017 ◽

Vol 71 ◽

pp. 413-420 ◽

Cited By ~ 12

Author(s):

Achinta Baidya ◽

Srimanta Baishya ◽

Trupti Ranjan Lenka

Keyword(s):

Double Gate ◽

High K ◽

Junctionless Transistor

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Impact of temperature on the performance of sub-35nm symmetric Double Gate Junctionless Transistor based inverter using High-K gate dielectric, a TCAD simulation study

2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES) ◽

10.1109/icpeices.2016.7853735 ◽

2016 ◽

Cited By ~ 1

Author(s):

Uttam Ch. Boro ◽

Nipanka Bora ◽

Pankaj Appun Pegu ◽

Rupaban Subadar

Keyword(s):

Simulation Study ◽

Gate Dielectric ◽

Double Gate ◽

High K ◽

Junctionless Transistor ◽

Tcad Simulation ◽

High K Gate Dielectric

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Performance assessment of symmetric double gate negative capacitance junctionless transistor with high-k spacer at elevated temperatures

Advances in Natural Sciences Nanoscience and Nanotechnology ◽

10.1088/2043-6254/ab3d2e ◽

2019 ◽

Vol 10 (3) ◽

pp. 035013

Author(s):

Hema Mehta ◽

Harsupreet Kaur

Keyword(s):

Performance Assessment ◽

Elevated Temperatures ◽

Negative Capacitance ◽

Double Gate ◽

High K ◽

Junctionless Transistor

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Performance analysis and improvement of nanoscale double gate Junctionless transistor based inverter using high-K gate dielectrics

TENCON 2015 - 2015 IEEE Region 10 Conference ◽

10.1109/tencon.2015.7373040 ◽

2015 ◽

Cited By ~ 3

Author(s):

Achinta Baidya ◽

T. R. Lenka ◽

S. Baishya

Keyword(s):

Performance Analysis ◽

Gate Dielectrics ◽

Double Gate ◽

High K ◽

Junctionless Transistor

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The impact of high-k gate dielectric on Junctionless Vertical Double Gate MOSFET

International Journal of Computer Sciences and Engineering ◽

10.26438/ijcse/v6i6.14751478 ◽

2018 ◽

Vol 6 (6) ◽

pp. 1475-1478

Author(s):

Jagdeep Rahul

Keyword(s):

Gate Dielectric ◽

Double Gate ◽

High K ◽

Double Gate Mosfet ◽

The Impact ◽

High K Gate Dielectric

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Design and Performance Analysis of Proposed Biosensor based on Double Gate Junctionless Transistor

Silicon ◽

10.1007/s12633-021-01335-6 ◽

2021 ◽

Author(s):

Pawandeep Kaur ◽

Avtar Singh Buttar ◽

Balwinder Raj

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Junctionless Transistor ◽

And Performance

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Analysis on Variations of Metal Gate Work Function on Junctionless Double Gate MOSFET with High-k Spacers

2020 International Conference on Emerging Trends in Communication, Control and Computing (ICONC3) ◽

10.1109/iconc345789.2020.9117425 ◽

2020 ◽

Author(s):

Gaurav Dhiman ◽

Rajeev Pourush

Keyword(s):

Work Function ◽

Double Gate ◽

Metal Gate ◽

High K ◽

Double Gate Mosfet ◽

Gate Work Function

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High-k Spacer Consideration of Ultrascaled Gate-All-Around Junctionless Transistor in Ballistic Regime

IEEE Transactions on Electron Devices ◽

10.1109/ted.2018.2873717 ◽

2018 ◽

Vol 65 (12) ◽

pp. 5282-5288

Author(s):

Yumei Yang ◽

Haijun Lou ◽

Xinnan Lin

Keyword(s):

Ballistic Regime ◽

High K ◽

Junctionless Transistor

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