Bio-inspired optimization for electromagnetic structure design using full-wave techniques on GPUs

2013 ◽  
Vol 26 (6) ◽  
pp. 649-669 ◽  
Author(s):  
O. Kilic ◽  
E. El-Araby ◽  
Q. Nguyen ◽  
V. Dang
Keyword(s):  
Structure Design ◽  
Electromagnetic Structure ◽  
Full Wave

Design Study of Dual Generated Radial Flux Permanent Magnet Generator for Pico Hydro Generator

2012 ◽  
Vol 212-213 ◽  
pp. 1025-1029
Author(s):  
Gyeong Chan Lee ◽  
Hoe Cheon Kim ◽  
Tae Uk Jung ◽  
Jang Mok Kim
Keyword(s):  
Permanent Magnet ◽  
High Efficiency ◽  
Acoustic Noise ◽  
Structure Design ◽  
Cogging Torque ◽  
Electromagnetic Structure ◽  
Radial Flux ◽  
High Output Voltage ◽  
Internal Rotor ◽  
Permanent Magnet Generator

The RFPM(Radial Flux Permanent Magnet) generator has numerous advantages such as high output voltage and output power, high efficiency, manufacture easy but the slotted RFPM generator configuration produces the cogging torque. The cogging torque would be the source of acoustic noise and vibration. This paper presents the electromagnetic structure design analysis and the cogging torque reduction design of RFPM generator. It is composed of the inner stator and the outer stator and internal rotor. We called it as DG-RFPMG(Dual Generator-Radial Flux Permanent Magnet Generator). Firstly, the design of the pole-arc ratio of rotor magnets to reduce cogging torque is studied. Secondly, the design of the stator displacement of the outer stator and the inner stator to reduce the cogging torque is studied. Finally, the combined design optimization considering both the pole- arc ratio and the stator displacement to reduce the cogging torque is studied. The design of DG-RFPMG was calculated by 2D FEM(Finite Element Method).

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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