Real-time classification performance and failure mode analysis of a physical/chemical sensor array and a probabilistic neural network

2001 ◽  
Vol 5 (5) ◽  
pp. 244-258 ◽  
Author(s):  
Sean J. Hart ◽  
Mark H. Hammond ◽  
Jennifer T. Wong ◽  
Mark T. Wright ◽  
Daniel T. Gottuk ◽  
...  
2020 ◽  
Vol 148 ◽  
pp. 111822 ◽  
Author(s):  
Jaeho Park ◽  
Yongrok Jeong ◽  
Jayoung Kim ◽  
Jimin Gu ◽  
Joseph Wang ◽  
...  

Author(s):  
Martin Versen ◽  
Dorina Diaconescu ◽  
Jerome Touzel

Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.


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