Low-complexity high-rate irregular QC-LDPC codes with applications to PR2 and EPR2 channels

2012 ◽  
Vol 25 (3) ◽  
pp. 370-382
Author(s):  
Virasit Imtawil ◽  
Mongkol Kupimai ◽  
Anan Kruesubthaworn ◽  
Apirat Siritaratiwat ◽  
Anupap Meesomboon
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
High Rate

Low-complexity girth-8 high-rate moderate length QC LDPC codes

2010 ◽  
Vol 64 (4) ◽  
pp. 360-365 ◽  
Author(s):  
M. Esmaeili ◽  
M.H. Tadayon ◽  
T.A. Gulliver
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
High Rate ◽  
Moderate Length

A Class of High-Rate Low-Complexity QC-LDPC Codes

2011 ◽  
Vol 30 (6) ◽  
pp. 1385-1389
Author(s):  
Long-jiang Jing ◽  
Jing-li Lin ◽  
Wei-le Zhu
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
High Rate

An Effective Low-Complexity Error-Floor Lowering Technique for High-Rate QC-LDPC Codes

2018 ◽  
Vol 22 (10) ◽  
pp. 1988-1991 ◽  
Author(s):  
Huang-Chang Lee ◽  
Po-Chiao Chou ◽  
Yeong-Luh Ueng
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
High Rate ◽  
Error Floor

scholarly journals Iterative Decoding of LDPC-Based Product Codes and FPGA-Based Performance Evaluation

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 122
Author(s):  
Weigang Chen ◽  
Wenting Zhao ◽  
Hui Li ◽  
Suolei Dai ◽  
Changcai Han ◽  
...  
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Iterative Decoding ◽  
Ldpc Codes ◽  
Low Complexity ◽  
High Rate ◽  
Error Floor ◽  
Product Codes ◽  
Field Programmable ◽  
Implementation Costs

Low-density parity-check (LDPC) codes have the potential for applications in future high throughput optical communications due to their significant error correction capability and the parallel decoding. However, they are not able to satisfy the very low bit error rate (BER) requirement due to the error floor phenomenon. In this paper, we propose a low-complexity iterative decoding scheme for product codes consisting of very high rate outer codes and LDPC codes. The outer codes aim at eliminating the residual error floor of LDPC codes with quite low implementation costs. Furthermore, considering the long simulation time of computer simulation for evaluating very low BER, the hardware platform is built to accelerate the evaluation of the proposed iterative decoding methods. Simultaneously, the fixed-point effects of the decoding algorithms are also be evaluated. The experimental results show that the iterative decoding of the product codes can achieve a quite low bit error rate. The evaluation using field programmable gate array (FPGA) also proves that product codes with LDPC codes and high-rate algebraic codes can achieve a good trade-off between complexity and throughput.

scholarly journals High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Cmos Technology ◽  
Area Efficiency ◽  
Prior Art ◽  
New Radio ◽  
High Area ◽  
Significant Area ◽  
Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

A Low-Complexity EMS Algorithm with Dynamic Message Truncation for Non-Binary LDPC Codes

2021 ◽  
Author(s):  
Fulong Wang ◽  
Ming Zhan ◽  
Qian Zhang ◽  
Hao Tang ◽  
Yunkai Feng ◽  
...  
Keyword(s):  
Ldpc Codes ◽  
Low Complexity

A Low-Complexity High-Rate Spatial Multiplexing Aided Generalized Spatial Modulation Scheme

2021 ◽  
Author(s):  
Yen-Ming Chen ◽  
Kuo-Chun Lin ◽  
Yao-Hsien Peng ◽  
Aswin Balaji ◽  
Chih-Peng Li
Keyword(s):  
Low Complexity ◽  
Spatial Multiplexing ◽  
Spatial Modulation ◽  
High Rate ◽  
Modulation Scheme
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