Systolic array implementation of 2-D digital filters using 2-D block processing

1990 ◽  
Vol 73 (8) ◽  
pp. 64-75 ◽  
Author(s):  
Yasuhiro Hirano ◽  
Tsuyoshi Takebe
Keyword(s):  
Systolic Array ◽  
Digital Filters ◽  
Block Processing

Reconfigurable systolic array implementation of quadratic digital filters

1986 ◽  
Vol 33 (8) ◽  
pp. 845-848 ◽  
Author(s):  
Hsing-Hsing Chiang ◽  
C. Nikias ◽  
A. Venetsanopoulos
Keyword(s):  
Systolic Array ◽  
Digital Filters

scholarly journals A Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters

VLSI Design ◽  
2002 ◽  
Vol 15 (2) ◽  
pp. 529-535
Author(s):  
A. T. Erdogan ◽  
T. Arslan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Filter ◽  
Digital Filters ◽  
Processing Algorithm ◽  
Block Processing ◽  
Segmentation Algorithms ◽  
Fir Digital Filters ◽  
Power Evaluation ◽  
Multiplier Circuit

A combined coefficient segmentation and block processing algorithm for low power implementation of FIR digital filters is described in this paper. The algorithm processes data and coefficients in blocks of fixed sizes. During the manipulation of each block, coefficients are segmented into two primitive components. The accumulative effect of processing a sequence of blocks and segmentation results in up to 80% reduction in power consumption in the multiplier circuit compared to conventional filtering. The paper describes the implementation of the algorithm, its constituent components, and the power evaluation environment developed. Simulations are performed using eight practical digital filter examples with various filter orders and data/coefficient wordlengths. In addition, the algorithm is compared with conventional filtering implementations and those using block processing and coefficient segmentation algorithms alone.

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