Lempel-Ziv-type high-speed data compression circuit using content addressable memory

1995 ◽  
Vol 78 (7) ◽  
pp. 60-67
Author(s):  
Akashi Satoh ◽  
Hideto Niijima
Keyword(s):  
Data Compression ◽  
High Speed ◽  
Content Addressable Memory ◽  
High Speed Data

scholarly journals GIF IMAGE HARDWARE COMPRESSORS

2021 ◽  
Author(s):  
Ivan Mozghovyi ◽  
Anatoliy Sergiyenko ◽  
Roman Yershov
Keyword(s):  
Data Compression ◽  
Data Storage ◽  
High Speed ◽  
Data Transfer ◽  
Future Research ◽  
Volume Data ◽  
High Speed Data ◽  
Lzw Algorithm ◽  
And Storage ◽  
Speed Data Transmission

Increasing requirements for data transfer and storage is one of the crucial questions now. There are several ways of high-speed data transmission, but they meet limited requirements applied to their narrowly focused specific target. The data compression approach gives the solution to the problems of high-speed transfer and low-volume data storage. This paper is devoted to the compression of GIF images, using a modified LZW algorithm with a tree-based dictionary. It has led to a decrease in lookup time and an increase in the speed of data compression, and in turn, allows developing the method of constructing a hardware compression accelerator during the future research.

scholarly journals Design and Implementation of a Lossless Serial High-Speed Data Compression System

2011 ◽  
pp. 1-4
Author(s):  
J. Sunil Kumar ◽  
G. Mahesh Kumar
Keyword(s):  
Data Compression ◽  
High Speed ◽  
Parallel Architecture ◽  
Vlsi Architecture ◽  
Data Networks ◽  
Compression Performance ◽  
High Data ◽  
High Speed Data ◽  
High Space ◽  
And Storage

The paper presents a novel VLSI architecture for high-speed data compressor designs which implement the X-Match algorithm. This design involves important trade off that affects the compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware. This device typical compression ratio that halves the original uncompressed data. This device is specifically targeted to enhance the performance of Gbits/s data networks and storage applications where it can double the performance of the original systems. To get high compression rate or to get high data rate of communication not restriction to follow the parallel architecture of data compression. By using existing method the main draw backs are 1. Variation in compression 2. Throughput, 3.Latency, 4.High space, 5. High power. So by using this proposed method we can reduce the variation in the compression, latency and increase through put. And this novel VLSI architecture has a power consumption of 81mwatts power

Sign in / Sign up

Export Citation Format

Share Document