Computer numerical analysis of the high-speed performance of a two-phase schottky barrier CCD with a metal shielding layer

1993 ◽  
Vol 76 (8) ◽  
pp. 61-71
Author(s):  
Kenji Yonei ◽  
Osamu Omoto
Keyword(s):  
Numerical Analysis ◽  
Schottky Barrier ◽  
High Speed ◽  
Two Phase ◽  
Speed Performance

scholarly journals Numerical Analysis of Dry Ice Blasting Convergent-Divergent Supersonic Nozzle

Energies ◽  
2019 ◽  
Vol 12 (24) ◽  
pp. 4787 ◽  
Author(s):  
Aleksandra Dzido ◽  
Piotr Krawczyk ◽  
Michalina Kurkus-Gruszecka
Keyword(s):  
Numerical Analysis ◽  
High Speed ◽  
Two Phase Flow ◽  
Supersonic Nozzle ◽  
Phase Flow ◽  
Two Phase ◽  
Dry Ice ◽  
Cleaning Methods ◽  
Industrial Cleaning ◽  
Dry Ice Blasting

There are several well-known and widely used industrial cleaning methods in the market today. One of them is dry ice blasting. In this method, moisture-free air is compressed, mixed with solid CO2 particles, and blasted though a nozzle; in the process, the gas expands, propelling its velocity. The high-speed, two-phase flow cleans by supercooling and crushing particles on the surface, causing dry ice sublimation. As the nozzle is a crucial component of the system, the authors conducted a numerical analysis of the geometry of the proposed convergent-divergent nozzle. A mathematical model of the supersonic, two-phase flow was developed and implemented in commercial Computational Fluid Dynamics (CFD) code. Various operating parameters, such as inlet pressure and dry ice mass flow, were taken into consideration.

NUMERICAL ANALYSIS OF DUAL TWO-PHASE DISCHARGE FROM A HEADER

2018 ◽  
Author(s):  
M. K. Guyot ◽  
Scott J. Ormiston ◽  
Hassan M. Soliman
Keyword(s):  
Numerical Analysis ◽  
Two Phase

Laser Silicon Interaction Study on Ring Oscillators to Establish Temperature Voltage Dependency Trends on 14 nm and Future FinFET Technologies

2017 ◽  
Author(s):  
Gaurav Mattey ◽  
Lava Ranganathan
Keyword(s):  
High Speed ◽  
Laser Frequency ◽  
Ring Oscillator ◽  
Switching Speed ◽  
Dual Nature ◽  
Voltage Imaging ◽  
Multiple Cores ◽  
Speed Performance ◽  
Self Test ◽  
Frequency Changes

Abstract Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Computation Time ◽  
Digital Signal ◽  
Instruction Set ◽  
Computationally Efficient ◽  
Specific Instruction ◽  
Processor Core ◽  
Speed Performance ◽  
Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

Two-Phase Short Circuit in the Power Grid Powered by a Transformer with a Y/Δ-11 Winding Connection

2020 ◽  
pp. 25-30
Author(s):  
Aleksandr S. Serebryakov ◽  
Vladimir L. Osokin ◽  
Sergey A. Kapustkin
Keyword(s):  
High Speed ◽  
Short Circuit ◽  
Relay Protection ◽  
Electric Circuit ◽  
Operational Reliability ◽  
Research Purpose ◽  
Industrial Complex ◽  
Two Phase ◽  
Short Circuit Currents ◽  
Secondary Winding

The article describes main provisions and relations for calculating short-circuit currents and phase currents in a three-phase traction transformer with a star-triangle-11 connection of windings, which feeds two single-phase loads in AC traction networks with a nominal voltage of 25 kilovolts. These transformers provide power to the enterprises of the agro-industrial complex located along the railway line. (Research purpose) The research purpose is in substantiating theoretical equations for digital intelligent relay protection in two-phase short circuits. (Materials and methods) It was found that since the sum of instantaneous currents in each phase is zero, each phase of the transformer works independently. We found that this significantly simplifies the task of analyzing processes with a two-phase short circuit. In this case, the problem of calculating short-circuit currents in the traction network can be simplified by reducing it to the calculation of an ordinary electric circuit with three unknown currents. (Results and discussion) The article describes equations for calculating short-circuit resistances for one phase of the transformer when connecting the secondary winding as a star or a triangle. The currents in the phases of the transformer winding at short circuit for the star-triangle-11 and star-star-with-ground schemes are compared. It was found that when calculating short-circuit currents, there is no need to convert the secondary winding of the traction transformer from a triangle to a star. (Conclusions) It was found that the results of the research can be used in the transition of relay protection systems from electromagnetic relays to modern high-speed digital devices, which will increase the operational reliability of power supply systems for traction and non-traction power consumers.

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