Positive feedback for gain enhancement in sub-100 nm multi-GHz CMOS amplifier design

2013 ◽  
Vol 43 (1) ◽  
pp. 111-124 ◽  
Author(s):  
Mark Pude ◽  
P. R. Mukund ◽  
Jeff Burleson
Keyword(s):  
Positive Feedback ◽  
Gain Enhancement ◽  
Amplifier Design ◽  
Cmos Amplifier

A 0.8 V CMOS amplifier design

2006 ◽  
Vol 47 (3) ◽  
pp. 315-321 ◽  
Author(s):  
C. Zhang ◽  
A. Srivastava ◽  
P. K. Ajmera
Keyword(s):  
Amplifier Design ◽  
Cmos Amplifier

scholarly journals A Positive Feedback-Based Op-Amp Gain Enhancement Technique for High-Precision Applications

2020 ◽  
Vol 29 (14) ◽  
pp. 2050220
Author(s):  
Rajasekhar Nagulapalli ◽  
Khaled Hayatleh ◽  
Steve Barker
Keyword(s):  
Positive Feedback ◽  
Cmos Technology ◽  
Voltage Gain ◽  
Silicon Area ◽  
Power Efficient ◽  
Enhancement Technique ◽  
Op Amp ◽  
Gain Enhancement ◽  
Pvt Variations ◽  
Boosting Technique

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65[Formula: see text]nm CMOS technology. It results in 81[Formula: see text]dB voltage gain, which is 21[Formula: see text]dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8[Formula: see text]V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1[Formula: see text]V supply. The circuit draws a total static current of 295[Formula: see text][Formula: see text]A and occupies 5000[Formula: see text][Formula: see text]m2 of silicon area.

Positive feedback technique and split‐length transistors for DC‐gain enhancement of two‐stage op‐amps

2017 ◽  
Vol 11 (6) ◽  
pp. 605-612 ◽  
Author(s):  
Seyed Mahmoud Anisheh ◽  
Hossein Shamsi ◽  
Mitra Mirhassani
Keyword(s):  
Positive Feedback ◽  
Two Stage ◽  
Gain Enhancement ◽  
Op Amps ◽  
Dc Gain
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