Efficient parallel implementations to compute the diameter of a graph

2020 ◽  
Author(s):  
Daisuke Takafuji ◽  
Koji Nakano ◽  
Yasuaki Ito
Keyword(s):  
Parallel Implementations

scholarly journals Parallel implementations of the False Nearest Neighbors method to study the behavior of dynamical models

2010 ◽  
Vol 52 (7-8) ◽  
pp. 1237-1242 ◽  
Author(s):  
I. Marín Carrión ◽  
E. Arias Antúnez ◽  
M.M. Artigao Castillo ◽  
J.J. Miralles Canals
Keyword(s):  
Nearest Neighbors ◽  
Dynamical Models ◽  
Parallel Implementations ◽  
False Nearest Neighbors

MicroBlaze-Based Multiprocessor Embedded Cryptosystem on FPGA for Elliptic Curve Scalar Multiplication Over Fp

2019 ◽  
Vol 28 (03) ◽  
pp. 1950037 ◽  
Author(s):  
A. Bellemou ◽  
N. Benblidia ◽  
M. Anane ◽  
M. Issad
Keyword(s):  
Elliptic Curve ◽  
Scalar Multiplication ◽  
Security Level ◽  
Prime Field ◽  
Montgomery Modular Multiplication ◽  
Parallel Implementations ◽  
High Radix ◽  
System On Programmable Chip ◽  
Xilinx Fpga ◽  
Elliptic Curve Scalar Multiplication

In this paper, we present Microblaze-based parallel architectures of Elliptic Curve Scalar Multiplication (ECSM) computation for embedded Elliptic Curve Cryptosystem (ECC) on Xilinx FPGA. The proposed implementations support arbitrary Elliptic Curve (EC) forms defined over large prime field ([Formula: see text]) with different security-level sizes. ECSM is performed using Montgomery Power Ladder (MPL) algorithm in Chudnovsky projective coordinates system. At the low abstraction level, Montgomery Modular Multiplication (MMM) is considered as the critical operation. It is implemented within a hardware Accelerator MMM (AccMMM) core based on the modified high radix, [Formula: see text] MMM algorithm. The efficiency of our parallel implementations is achieved by the combination of the mixed SW/HW approach with Multi Processor System on Programmable Chip (MPSoPC) design. The integration of multi MicroBlaze processor in single architecture allows not only the flexibility of the overall system but also the exploitation of the parallelism in ECSM computation with several degrees. The Virtex-5 parallel implementations of 256-bit and 521-bis ECSM computations run at 100[Formula: see text]MHZ frequency and consume between 2,739 and 6,533 slices, 22 and 72 RAMs and between 16 and 48 DSP48E cores. For the considered security-level sizes, the delays to perform single ECSM are between 115[Formula: see text]ms and 14.72[Formula: see text]ms.

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