Area‐efficient and high‐speed hardware structure of hybrid cryptosystem (AES‐RC4) for maximizing key lifetime using parallel subpipeline architecture

Author(s):  
Senthil Murugan Maniam ◽  
T. Sasilatha
Author(s):  
A. Arunkumar Gudivada ◽  
K. Jayaram Kumar ◽  
Srinivasa Rao Jajula ◽  
Durga Prasad Siddani ◽  
Praveen Kumar Poola ◽  
...  

2020 ◽  
Vol 14 (4) ◽  
pp. 450-458
Author(s):  
Piyush Tyagi ◽  
Rishikesh Pandey

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