Adaptive TB-LMI: An efficient memory controller and scheduler design

2018 ◽  
Vol 31 (7) ◽  
pp. e5011 ◽  
Author(s):  
A.A. El-Moursy ◽  
A.S. Elhelw
Keyword(s):  
Memory Controller ◽  
Efficient Memory ◽  
Scheduler Design

scholarly journals CONCEPT: A Column Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM

2020 ◽  
Author(s):  
Nishil Talati ◽  
Heonjae Ha ◽  
Ben Perach ◽  
Ronny Ronen ◽  
Shahar Kvatinsky
Keyword(s):  
Energy Efficiency ◽  
State Of The Art ◽  
Full Potential ◽  
Performance Gain ◽  
Memory Controller ◽  
Von Neumann ◽  
Technology Node ◽  
Data Intensive ◽  
Computing Model ◽  
Efficient Memory

While DRAM cannot easily scale below a 20nm technology node, RRAM suffers far less from scalability issues. Moreover, RRAM’s resistivity enables its use for processing-in-memory (PIM), potentially alleviating the von Neumann bottleneck. Unfortunately, because of technological idiosyncrasies, existing DRAM-centric memory controllers cannot exploit the full potential of RRAM. In this paper, we present the design of a memory controller called CONCEPT. The controller is optimized to exploit unique properties of RRAM to enhance its performance and energy efficiency as well as exploiting RRAM’s PIM capability. We show that with CONCEPT, RRAM can achieve DRAM-like performance and energy efficiency on SPEC CPU 2006 benchmarks. Furthermore, using RRAM PIM capabilities, we show a 5X performance gain on a data-intensive in-memory database workload compared to a state-of-the-art CPU-memory computing model.

scholarly journals CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM

IEEE Micro ◽  
2019 ◽  
Vol 39 (1) ◽  
pp. 33-43 ◽  
Author(s):  
Nishil Talati ◽  
Heonjae Ha ◽  
Ben Perach ◽  
Ronny Ronen ◽  
Shahar Kvatinsky
Keyword(s):  
Memory Controller ◽  
Efficient Memory

scholarly journals CONCEPT: A Column Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM

2020 ◽  
Author(s):  
Nishil Talati ◽  
Heonjae Ha ◽  
Ben Perach ◽  
Ronny Ronen ◽  
Shahar Kvatinsky
Keyword(s):  
Energy Efficiency ◽  
State Of The Art ◽  
Full Potential ◽  
Performance Gain ◽  
Memory Controller ◽  
Von Neumann ◽  
Technology Node ◽  
Data Intensive ◽  
Computing Model ◽  
Efficient Memory

While DRAM cannot easily scale below a 20nm technology node, RRAM suffers far less from scalability issues. Moreover, RRAM’s resistivity enables its use for processing-in-memory (PIM), potentially alleviating the von Neumann bottleneck. Unfortunately, because of technological idiosyncrasies, existing DRAM-centric memory controllers cannot exploit the full potential of RRAM. In this paper, we present the design of a memory controller called CONCEPT. The controller is optimized to exploit unique properties of RRAM to enhance its performance and energy efficiency as well as exploiting RRAM’s PIM capability. We show that with CONCEPT, RRAM can achieve DRAM-like performance and energy efficiency on SPEC CPU 2006 benchmarks. Furthermore, using RRAM PIM capabilities, we show a 5X performance gain on a data-intensive in-memory database workload compared to a state-of-the-art CPU-memory computing model.

scholarly journals Linear capabilities for fully abstract compilation of separation-logic-verified code

2021 ◽  
Vol 31 ◽  
Author(s):  
THOMAS VAN STRYDONCK ◽  
FRANK PIESSENS ◽  
DOMINIQUE DEVRIESE
Keyword(s):  
Spatial Separation ◽  
Separation Logic ◽  
Target Language ◽  
Fine Grained ◽  
Dynamic Contract ◽  
Modular Verification ◽  
Source Program ◽  
Memory Accesses ◽  
Memory Resources ◽  
Efficient Memory

Abstract Separation logic is a powerful program logic for the static modular verification of imperative programs. However, dynamic checking of separation logic contracts on the boundaries between verified and untrusted modules is hard because it requires one to enforce (among other things) that outcalls from a verified to an untrusted module do not access memory resources currently owned by the verified module. This paper proposes an approach to dynamic contract checking by relying on support for capabilities, a well-studied form of unforgeable memory pointers that enables fine-grained, efficient memory access control. More specifically, we rely on a form of capabilities called linear capabilities for which the hardware enforces that they cannot be copied. We formalize our approach as a fully abstract compiler from a statically verified source language to an unverified target language with support for linear capabilities. The key insight behind our compiler is that memory resources described by spatial separation logic predicates can be represented at run time by linear capabilities. The compiler is separation-logic-proof-directed: it uses the separation logic proof of the source program to determine how memory accesses in the source program should be compiled to linear capability accesses in the target program. The full abstraction property of the compiler essentially guarantees that compiled verified modules can interact with untrusted target language modules as if they were compiled from verified code as well. This article is an extended version of one that was presented at ICFP 2019 (Van Strydonck et al., 2019).

scholarly journals Study on the Implementation of a Simple and Effective Memory System for an AI Chip

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1399
Author(s):  
Taepyeong Kim ◽  
Sangun Park ◽  
Yongbeom Cho
Keyword(s):  
High Speed ◽  
Memory Systems ◽  
Memory System ◽  
External Memory ◽  
Essential Factor ◽  
Wide Bandwidth ◽  
Reading And Writing ◽  
Data Skew ◽  
Lower Performance ◽  
Efficient Memory

In this study, a simple and effective memory system required for the implementation of an AI chip is proposed. To implement an AI chip, the use of internal or external memory is an essential factor, because the reading and writing of data in memory occurs a lot. Those memory systems that are currently used are large in design size and complex to implement in order to handle a high speed and a wide bandwidth. Therefore, depending on the AI application, there are cases where the circuit size of the memory system is larger than that of the AI core. In this study, SDRAM, which has a lower performance than the currently used memory system but does not have a problem in operating AI, was used and all circuits were implemented digitally for simple and efficient implementation. In particular, a delay controller was designed to reduce the error due to data skew inside the memory bus to ensure stability in reading and writing data. First of all, it verified the memory system based on the You Only Look Once (YOLO) algorithm in FPGA to confirm that the memory system proposed in AI works efficiently. Based on the proven memory system, we implemented a chip using Samsung Electronics’ 65 nm process and tested it. As a result, we designed a simple and efficient memory system for AI chip implementation and verified it with hardware.

scholarly journals Knowledge-Assisted Deep Reinforcement Learning in 5G Scheduler Design: From Theoretical Framework to Implementation

2021 ◽  
pp. 1-1
Author(s):  
Zhouyou Gu ◽  
Changyang She ◽  
Wibowo Hardjawana ◽  
Simon Lumb ◽  
David McKechnie ◽  
...  
Keyword(s):  
Reinforcement Learning ◽  
Theoretical Framework ◽  
Scheduler Design

A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation

2016 ◽  
Vol 63 (7) ◽  
pp. 668-672
Author(s):  
Shouyi Yin ◽  
Peng Ouyang ◽  
Leibo Liu ◽  
Shaojun Wei
Keyword(s):  
Power Efficient ◽  
Efficient Memory
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