An acceleration of quasigroup operations by residue arithmetic

2017 ◽  
Vol 30 (2) ◽  
pp. e4239 ◽  
Author(s):  
Pavel Krömer ◽  
Jan Platoš ◽  
Jana Nowaková ◽  
Václav Snášel
Keyword(s):  
Residue Arithmetic

scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic Circuits

2003 ◽  
Vol 12 (01) ◽  
pp. 41-53 ◽  
Author(s):  
Shugang Wei ◽  
Kensuke Shimizu
Keyword(s):  
Real Time ◽  
Error Detection ◽  
Binary Tree ◽  
Word Length ◽  
Arithmetic Circuits ◽  
Binary Number ◽  
Residue Number ◽  
Residue Arithmetic ◽  
Large Product ◽  
Binary Tree Structure

This paper presents a fast residue checker for the error detection of arithmetic circuits. The residue checker consists of a number of residue arithmetic circuits such as adders, multipliers and binary-to-residue converters based on radix-two signed-digit (SD) number arithmetic. The proposed modulo m (m = 2p ± 1) adder is designed with a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. The modulo m multiplier and binary-to-residue number converter are constructed with a binary tree structure of the modulo m SD adders. Thus, the modulo m multiplication is performed in a time proportional to log 2 p and an n-bit binary number is converted into a p-digit SD residue number, n ≫ p, in a time proportional to log 2(n/p). By using the presented residue arithmetic circuits, the error detection can be performed in real-time for a large product-sum circuit.

Residue Arithmetic Algorithms for Exact Computation ofg-Inverses of Matrices

1976 ◽  
Vol 13 (2) ◽  
pp. 155-171 ◽  
Author(s):  
T. Mahadeva Rao ◽  
K. Subramanian ◽  
E. V. Krishnamurthy
Keyword(s):  
Exact Computation ◽  
Residue Arithmetic
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