Design of a high precision logarithmic converter in a binary floating point divider

2010 ◽  
Vol 24 (4) ◽  
pp. 342-353 ◽  
Author(s):  
Yong-Hwan Lee ◽  
Young-Sung Cho ◽  
Sangook Moon
Author(s):  
Dongdong Chen ◽  
Yu Zhang ◽  
Younhee Choi ◽  
Moon Ho Lee ◽  
Seok-Bum Ko

2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Anitha Juliette Albert ◽  
Seshasayanan Ramachandran

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.


Integration ◽  
2017 ◽  
Vol 59 ◽  
pp. 247-254 ◽  
Author(s):  
Zongwei Li ◽  
Xingyin Xiong ◽  
Xiong Liu ◽  
Kedu Han ◽  
Ning Cong ◽  
...  

2012 ◽  
Vol 61 (5) ◽  
pp. 607-621 ◽  
Author(s):  
Dongdong Chen ◽  
Liu Han ◽  
Younhee Choi ◽  
Seok-Bum Ko

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