scholarly journals Hardware Implementation of Neuromorphic Computing Using Large‐Scale Memristor Crossbar Arrays

2020 ◽  
pp. 2000137 ◽  
Author(s):  
Yesheng Li ◽  
Kah-Wee Ang
Keyword(s):  
Large Scale ◽  
Hardware Implementation ◽  
Neuromorphic Computing ◽  
Memristor Crossbar

scholarly journals A Memristor-Based Cascaded Neural Networks for Specific Target Recognition

2019 ◽  
Author(s):  
Sheng-Yang Sun ◽  
Hui Xu ◽  
Jiwei Li ◽  
Yi Sun ◽  
Qingjiang Li ◽  
...  
Keyword(s):  
Large Scale ◽  
Recognition Accuracy ◽  
Circuit Simulation ◽  
High Yield ◽  
Small Scale ◽  
Neuromorphic Computing ◽  
Split Method ◽  
High Recognition Accuracy ◽  
Memristor Crossbar ◽  
Computational Ability

Multiply-accumulate calculations using a memristor crossbar array is an important method to realize neuromorphic computing. However, the memristor array fabrication technology is still immature, and it is difficult to fabricate large-scale arrays with high-yield, which restricts the development of memristor-based neuromorphic computing technology. Therefore, cascading small-scale arrays to achieve the neuromorphic computational ability that can be achieved by large-scale arrays, which is of great significance for promoting the application of memristor-based neuromorphic computing. To address this issue, we present a memristor-based cascaded framework with some basic computation units, several neural network processing units can be cascaded by this means to improve the processing capability of the dataset. Besides, we introduce a split method to reduce pressure of input terminal. Compared with VGGNet and GoogLeNet, the proposed cascaded framework can achieve 93.54% Fashion-MNIST accuracy under the 4.15M parameters. Extensive experiments with Ti/AlOx/TaOx/Pt we fabricated are conducted to show that the circuit simulation results can still provide a high recognition accuracy, and the recognition accuracy loss after circuit simulation can be controlled at around 0.26%.

Large-Scale and Flexible Optical Synapses for Neuromorphic Computing and Integrated Visible Information Sensing Memory Processing

ACS Nano ◽  
2020 ◽  
Author(s):  
Ya-Xin Hou ◽  
Yi Li ◽  
Zhi-Cheng Zhang ◽  
Jia-Qiang Li ◽  
De-Han Qi ◽  
...  
Keyword(s):  
Large Scale ◽  
Neuromorphic Computing ◽  
Memory Processing

Memristor Crossbar-Based Neuromorphic Computing System: A Case Study

2014 ◽  
Vol 25 (10) ◽  
pp. 1864-1878 ◽  
Author(s):  
Miao Hu ◽  
Hai Li ◽  
Yiran Chen ◽  
Qing Wu ◽  
Garrett S. Rose ◽  
...  
Keyword(s):  
Computing System ◽  
Neuromorphic Computing ◽  
System A ◽  
Memristor Crossbar

scholarly journals Smooth Nonlinear Fitting Scheme for Analog Multiplierless Implementation of Hindmarsh-Rose Neuron Model

2021 ◽  
Author(s):  
Jianming Cai ◽  
Han Bao ◽  
Quan Xu ◽  
Zhongyun Hua ◽  
Bocheng Bao
Keyword(s):  
Large Scale ◽  
Neuron Model ◽  
Hardware Implementation ◽  
Three Dimensional ◽  
Two Dimensional ◽  
Implementation Cost ◽  
Hyperbolic Tangent ◽  
Nonlinear Fitting ◽  
Chaotic Bursting ◽  
Electrical Activities

Abstract The Hindmarsh-Rose (HR) neuron model is built to describe the neuron electrical activities. Due to the polynomial nonlinearities, multipliers are required to implement the HR neuron model in analog. In order to avoid the multipliers, this brief presents a novel smooth nonlinear fitting scheme. We first construct two nonlinear fitting functions using the composite hyperbolic tangent functions and then implement an analog multiplierless circuit for the two-dimensional (2D) or three- dimensional (3D) HR neuron model. To exhibit the nonlinear fitting effects, numerical simulations and hardware experiments for the fitted HR neuron model are provided successively. The results show that the fitted HR neuron model with analog multiplierless circuit can display different operation patterns of resting, periodic spiking, and periodic/chaotic bursting, entirely behaving like the original HR neuron model. The analog multiplierless circuit has the advantage of low implementation cost and thereby it might be suitable for the hardware implementation of large-scale neural networks.

scholarly journals Quantum Tunnelling based Ultra-compact and Energy Efficient Spiking Neuron enables Hardware Liquid State Machine

2021 ◽  
Author(s):  
Ajay Singh ◽  
Vivek Saraswat ◽  
Maryam Shojaei Baghini ◽  
Udayan Ganguly
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Hardware Implementation ◽  
Cmos Technology ◽  
Quantum Tunnelling ◽  
Low Area ◽  
Standby Power ◽  
Similar Area ◽  
First Time ◽  
Lif Neuron

Abstract Low-power and low-area neurons are essential for hardware implementation of large-scale SNNs. Various novel physics based leaky-integrate-and-fire (LIF) neuron architectures have been proposed with low power and area, but are not compatible with CMOS technology to enable brain scale implementation of SNN. In this paper, for the first time, we demonstrate hardware implementation of LSM reservoir using band-to-band-tunnelling (BTBT) based neuron. A low-power thresholding circuit and current-to-voltage converter design are proposed. We further propose a predistortion technique to linearize a nonlinear neuron without any area and power overhead. We establish the equivalence of the proposed neuron with the ideal LIF neuron to demonstrate its versatility. To verify the effect of the proposed neuron, a 36-neuron LSM reservoir is fabricated in GF-45nm PDSOI technology. We achieved 5000x lower energy-per-spike at a similar area, 50x less area at a similar energy-per-spike, and 10x lower standby power at a similar area and energy-per-spike. Such overall performance improvement enables brain scale computing.

Achieving Complementary Resistive Switching and Multi-bit Storage Goals by Modulating Dual-ion Reaction through Supercritical Fluid-assisted Ammoniation

Nanoscale ◽  
2021 ◽  
Author(s):  
Lei Li ◽  
Tianjiao Dai ◽  
Kuan-Chang Chang ◽  
Rui Zhang ◽  
Xinnan Lin ◽  
...  
Keyword(s):  
Supercritical Fluid ◽  
Resistive Switching ◽  
Neuromorphic Computing ◽  
Crossbar Array ◽  
Memristor Crossbar

Complementary resistive switching (CRS) is a core requirement in memristor crossbar array construction for neuromorphic computing in view of its capability to avoid sneak path current. However, previous approaches to...

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