Skin-Inspired Haptic Memory Arrays with an Electrically Reconfigurable Architecture

2015 ◽  
Vol 28 (8) ◽  
pp. 1559-1566 ◽  
Author(s):  
Bowen Zhu ◽  
Hong Wang ◽  
Yaqing Liu ◽  
Dianpeng Qi ◽  
Zhiyuan Liu ◽  
...  
Keyword(s):  
Reconfigurable Architecture ◽  
Memory Arrays ◽  
Haptic Memory

scholarly journals Memory Arrays: Skin-Inspired Haptic Memory Arrays with an Electrically Reconfigurable Architecture (Adv. Mater. 8/2016)

2016 ◽  
Vol 28 (8) ◽  
pp. 1526-1526 ◽  
Author(s):  
Bowen Zhu ◽  
Hong Wang ◽  
Yaqing Liu ◽  
Dianpeng Qi ◽  
Zhiyuan Liu ◽  
...  
Keyword(s):  
Reconfigurable Architecture ◽  
Memory Arrays ◽  
Haptic Memory

HyDRA: Hybrid Dynamically Reconfigurable Architecture for DSP Applications

2016 ◽  
Vol E99.C (7) ◽  
pp. 866-877 ◽  
Author(s):  
Abdulfattah M. OBEID ◽  
Syed Manzoor QASIM ◽  
Mohammed S. BENSALEH ◽  
Abdullah A. ALJUFFRI
Keyword(s):  
Reconfigurable Architecture ◽  
Dynamically Reconfigurable ◽  
Dsp Applications ◽  
Dynamically Reconfigurable Architecture

Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC© Microprocessor

2006 ◽  
Author(s):  
Ray Talacka ◽  
Nandu Tendolkar ◽  
Cynthia Paquette
Keyword(s):  
High Performance ◽  
Yield Enhancement ◽  
Test Time ◽  
Balance Test ◽  
Specific Test ◽  
Defect Location ◽  
Test Methodology ◽  
Memory Arrays ◽  
Scan Chain ◽  
Scan Pattern

Abstract The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.

Modular Reconfigurable Architecture for Tailored Rapid SE Artifact

2010 ◽  
Author(s):  
Stas Tarchalski ◽  
Sue O'Brien ◽  
Dawn Sabados ◽  
Julie Fortune ◽  
Phillip Alldredge ◽  
...  
Keyword(s):  
Reconfigurable Architecture

scholarly journals Workload-aware Electromigration Analysis in Emerging Spintronic Memory Arrays

2021 ◽  
pp. 1-1
Author(s):  
Sarath Mohanachandran Nair ◽  
Mahta Mayahinia ◽  
Mehdi B. Tahoori ◽  
Manu Perumkunnil ◽  
Houman Zahedmanesh ◽  
...  
Keyword(s):  
Memory Arrays
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